MCS-202 Solved Assignment January 2026 | Computer Organisation | IGNOU BCA_NEWOL

Q: Question 1: (Covers Block1)

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Q: Question 4: (Covers Block 4)

The 8086 microprocessor is a foundational architecture in computer organization, characterized by its segmented memory addressing and a comprehensive set of flags that indicate processor status and control operations. Its design includes an Interrupt Vector Table for efficient handling of various interrupt types and supports assembly language programming for direct hardware interaction. Modern computing extends these concepts with advanced architectures like pipelining, vector processing, multi-

Q1. Question 1: (Covers Block1)

(a)) Explain the von Neumann architecture with the help of a diagram. Also, explain how the data and instructions are stored in this architecture. (300 words)
(b)) Explain how a computer will execute the following high-level language program segment: int x=10, y=20, result; result=x+y; (300 words)
(c)) Perform the following conversion of numbers: (i) Decimal (1479865320)10 to binary and hexadecimal. (ii) Hexadecimal (BCDAFD01)h to binary and Octal. (iii) ASCII String "BCA Programme Code is BCA_NEW & BCA_NEWOL" to UTF-8 (iv) Octal (72143065)o to Decimal (300 words)
(d)) Simplify the following function using a K-map: F(A, B, C, D) = Σ (1,3, 4, 5, 7, 11, 12). Draw the circuit for the simplified function using NAND gates. (300 words)
(e)) Consider the Adder-Subtractor circuit given in Unit 3 of Block 1. Explain how this circuit will perform subtraction (A-B) if the value of A is 1001 and B is 0111. You must list all the bit values, including Cin, Cout, and the overflow condition. (300 words)
(f)) Make the Truth Table and draw the logic diagram of a 3×8 decoder. Explain its functioning with the help of a truth table and an example input. (300 words)
(g)) Assume that a source data value 1011 was received at a destination as 0011. Show how Hamming's Error-Correcting code will be appended to the source data, so this one-bit error is identified and corrected at the destination. You may assume that the transmission error occurs in the source data and not in the error correction code. (300 words)
(h)) Explain the functioning of the RS flip-flop with the help of a logic diagram and a characteristic table. Also, make and explain the excitation table of this flip-flop. (300 words)
(i)) Explain the functioning of a synchronous counter. (300 words)
(j)) Represent (-729.25)10 and (0.0078125)10 in IEEE 754 single precision format. (300 words)

Key Points:

Von Neumann architecture unifies data/instructions in single memory, executed sequentially by CPU.
High-level code compiles to machine instructions for memory allocation, data loading, ALU operations.
Number system conversions (Decimal, Binary, Hex, Octal) use division/multiplication or bit grouping.
K-map simplifies Boolean functions (SOP) into minimal terms, then implemented with NAND gates.

Answer:

Q2. Question 2: (Covers Block 2)

(a)) (i) Explain the structure of a 4×2 ROM with the help of a diagram. (ii) How many memory chips of size 128K x 8bits are needed to build a RAM of size 64 M words if the word size of RAM is 32 bits? (iii) Find the storage capacity of a Magnetic disk with 16 recording surfaces, and 256 tracks consisting of 256 sectors each. You may assume that each sector can store 1 MB of data. (iv) Find the rotational latency of a disk that rotates at 9000 rpm. (300 words)
(b)) Consider that the main memory of a computer is 256 words (assume a memory word to be 32 bits). The cache memory of this computer consists of 8 blocks, each 128 bits in size. Find the cache addresses for the main memory addresses 011000112 and 110101112 for the following cache mapping schemes: (i) Associative cache mapping (ii) Direct cache mapping (iii) Two-way set-associative cache mapping (300 words)
(c)) Explain the steps of a Direct Memory Access (DMA) transfer. What are the advantages of using the DMA technique of data transfer? Illustrate the DMA breakpoints in an instruction cycle with the help of a diagram. (300 words)
(d)) What is an interrupt? Explain the steps of interrupt processing with the help of a diagram. Explain the design issues for implementing interrupt-driven Input/Output (I/O). (300 words)
(e)) Explain the features of the following I/O Technologies: (i) Active-Matrix Liquid Crystal Displays (ii) Colour Depth in the context of Video cards (iii) Scanners (iv) Non-impact printers (300 words)

Key Points:

4x2 ROM uses 2-to-4 decoder and OR gates to select and output a 2-bit word.
RAM chip calculation involves dividing total bits by chip bits, considering both word width and capacity.
Magnetic disk capacity is product of surfaces, tracks, sectors, and data per sector.
Rotational latency is half the time for one full disk revolution.

Answer: This comprehensive response addresses various aspects of computer organization as covered in Block 2 of the MCS-202 course. It delves into memory structures, storage capacity calculations, cache mapping techniques, data transfer mechanisms like DMA, interrupt processing, and features of modern I/O technologies. Each section provides detailed explanations, step-by-step calculations, and descriptions of conceptual diagrams, adhering to the specified word limits and formatting guidelines. Memory o...

Q3. Question 3: (Covers Block 3)

(a)) Explain the functioning of subroutine call and return instructions with the help of an example. Also, explain indirect addressing, indexed addressing, and stack addressing with the help of an example for each. (300 words)
(b)) Demonstrate how the size of a machine program changes for the computation of the expression result=(a+b) * (a*b+c) when the instruction sets have (i) zero address instructions, (ii) one address instructions, (iii) two address instructions, and (iv) three address instructions. (300 words)
(c)) Consider a machine that uses PC, IR, AC, and MAR registers to execute different instructions. All the memory accesses during instruction execution bring data to a temporary register named TR. The ALU of the machine performs the subtraction operation using the AC and TR registers, and the result of the subtraction operation is stored in the AC register. List and explain all the microoperations required to execute the following machine instruction: AC ← AC -M; where M is the address of a direct operand in the Memory Assume that PC is currently pointing to this instruction. Make and state suitable assumptions, if any. (300 words)
(d)) Explain the operation of a micro-programmed control unit with the help of a diagram. (300 words)
(e)) What are the features of a RISC machine? Explain the RISC pipelining with the help of a diagram. (300 words)

Key Points:

Subroutine calls push return address onto stack; returns pop it to resume execution.
Indirect addressing points to operand's address; Indexed addressing adds register content to base address.
Stack addressing implicitly uses stack top for operands; zero-address instructions.
Instruction size (0 to 3 address) inversely affects program instruction count for an expression.

Answer: This comprehensive response addresses various fundamental aspects of computer organization, specifically focusing on instruction execution, addressing modes, instruction set architectures, and control unit design, as covered in Block 3 of the MCS-202 course. It delves into the mechanics of subroutine calls, different addressing techniques, and the impact of instruction formats on program size. Furthermore, it details the microoperations involved in executing an instruction and explains the opera...

Q4. Question 4: (Covers Block 4)

(a)) What is a Flag register in the 8086 microprocessor? Explain any four flags and their use. What is the need for a segment register in the 8086 microprocessor? Compute the physical address for the following {Segment Register : Offset} pairs in an 8086 microprocessor: (i) CS: IP = ABCDh:AAFFh (ii) DS:BX = 1FBHh:99FFh (iii) SS: SP = EFFFh: 00ABh (300 words)
(b)) What is an Interrupt Vector Table (IVT) in the 8086 microprocessor? Explain its use with the help of a diagram. Write a program using 8086 assembly language to input a string: "Welcome to the Programme." (300 words)
(c)) Write a program in 8086 assembly language that converts a 4-bit unsigned binary number to an equivalent unpacked BCD value. For example, the input binary number 11012 is first converted to its equivalent BCD value, 13, i.e., 000100112. This value is then unpacked and stored as unpacked BCD values, 000000012 and 000000112. Explain the algorithm of the program. (300 words)
(d)) Explain the features and advantages of the following: (i) Pipeline for adding two floating-point numbers (ii) Vector Processing (iii) Bus interconnection structure in a multiprocessor system (iv) Multi-core processors (v) Inter-processor communication and synchronisation (300 words)

Key Points:

8086 Flag Register: 16-bit, indicates operation results, controls processor; e.g., CF, ZF, SF, OF for arithmetic status.
8086 Segment Registers: Overcome 16-bit register limit to address 1MB memory; Physical Address = (Segment << 4) + Offset.
Interrupt Vector Table (IVT): First 1KB memory, 256 entries (4 bytes each, CS:IP) for ISR addresses.
Unpacked BCD Conversion: Binary number divided by 10 yields tens (quotient) and units (remainder) as unpacked BCD.

Answer: The 8086 microprocessor is a foundational architecture in computer organization, characterized by its segmented memory addressing and a comprehensive set of flags that indicate processor status and control operations. Its design includes an Interrupt Vector Table for efficient handling of various interrupt types and supports assembly language programming for direct hardware interaction. Modern computing extends these concepts with advanced architectures like pipelining, vector processing, multi-...

MCS-202 Solved Assignment — January 2026 / July 2026

Computer Organisation | IGNOU Bachelor of Computer Applications (BCA_NEWOL)

MCS-202—January 2026 / July 2026

Computer Organisation

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MCS-202 Assignment Questions — January 2026

Q1. Question 1: (Covers Block1)

Q2. Question 2: (Covers Block 2)

Q3. Question 3: (Covers Block 3)

Q4. Question 4: (Covers Block 4)