MCS-012 Solved Assignment January 2026 | Computer Organisation and Assembly Language Programming | IGNOU BCA

Q: Explain the following, giving their uses and advantages/disadvantages, if needed. (Word limit for the answer of each part is 50 words ONLY)

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Q1(a). Please refer to Figure 4 of Unit 1 of Block 1 on page 11 of the Instruction execution example. Assuming a similar machine is to be used for the execution of the following three consecutive instructions: LOAD A; Load the content of Memory location A into the Accumulator Register. SUBT B; Subtract the content of memory location B from the Accumulator Register. STOR C; Stores the content of the Accumulator register to memory location C. However, this machine is different from the example in Figure 4 in the following ways: Each memory word of this new machine is 16 bits long. Each instruction is of length 16 bits with 4 bits for the operation code (opcode) and 12 bits for specifying one direct operand. The size of an operand is 16 bits. The Main Memory of the machine is of size 212 words. The three consecutive instructions are placed starting from memory location (10F)h ; operand A is at location (2FF)h and contains a value (2AC5)h, Operand B is at location (300)h and contains a value (1AEE)h and operand C is at location (301)h and contains a value (00000)h. The AC, IR, MAR and MBR registers are of size 16 bits, whereas the PC register is of size 12 bits. The initial content of the PC register is (10E)h.

(i)) Draw a diagram showing the Initial State of the machine with the addresses and content of memory locations in hexadecimal. Show only those address locations of the memory that store instructions and data. Also, show the content of all the stated registers. (120 words)
(ii)) Draw three more diagrams, each showing the state of the machine after execution of every instruction, viz. LOAD, SUBT and STOR. Show the changes in the values of Registers and memory locations, if any, due to the execution of the instruction. Show all the addresses and values in hexadecimal notation. (180 words)

Key Points:

Machine architecture: 16-bit words, 4-bit opcode, 12-bit direct operand address.
Instruction cycle: Fetch (MAR←PC, PC←PC+1, MBR←M[MAR], IR←MBR) and Execute phases.
Register functions: PC for next instruction, AC for arithmetic, IR for current instruction, MAR for memory address, MBR for memory data.
Hexadecimal arithmetic is vital for accurate data manipulation (e.g., subtraction).

Answer: The execution of instructions in a computer system involves a series of micro-operations that update the state of various registers and memory locations. This process is governed by the instruction cycle, which typically consists of fetch, decode, and execute phases. The provided scenario describes a custom machine, requiring the simulation of this cycle for three consecutive instructions: LOAD, SUBT, and STOR. Understanding the machine's architecture, including word size, instruction format, an...

Q1(b). Perform the following conversion of numbers:

i)) Decimal (269785421)10 to binary and hexadecimal. (75 words)
ii)) Hexadecimal (8FACBED34)h into Octal. (75 words)
iii)) String "lowercase vs UPPERCASE” into UTF-8. (75 words)
iv)) Octal (65874531)o into Decimal. (75 words)

Key Points:

Decimal to binary uses successive division by 2, remainders collected in reverse.
Decimal to hexadecimal uses successive division by 16, collecting hex digits in reverse.
Hexadecimal to octal requires intermediate conversion to binary for grouping.
UTF-8 for ASCII characters (0-127) uses one byte, identical to ASCII values.

Answer: Number system conversions are fundamental operations in Computer Organization, allowing data representation across various bases like decimal, binary, octal, and hexadecimal. Understanding these conversions, as covered in MCS-012, is crucial for grasping how computers store and process information. The following sections detail the conversions as requested, adhering to standard methods and terminology.

Q2(a). Refer to the Figure 2(b) on page 8 in Unit 1 of Block 2. Draw the Internal organisation of an 8×4 RAM. Explain all the inputs and outputs of this organisation. Also, answer the following:

(i)) How many data input and data output lines does this RAM need? Explain your answer. (150 words)
(ii)) How many address lines are needed for this RAM? Give reasons in support of your answer. (150 words)

Key Points:

An 8x4 RAM stores 8 words, each 4 bits in size.
Internal organization includes memory array, address decoder, I/O buffers, and control logic.
It requires 4 data input lines and 4 data output lines for 4-bit word operations.
Three address lines are essential to uniquely select one of the 8 memory locations (2³ = 8).

Answer: An 8×4 RAM, as conceptually depicted in Figure 2(b) of Unit 1, Block 2, is organized to store 8 words, with each word being 4 bits long. Its internal structure comprises several key components that facilitate data storage and retrieval. At its core is a memory array, arranged as 8 rows (memory locations) and 4 columns (bits per word). This array consists of individual memory cells, typically latches or flip-flops, capable of storing a single bit. Each row represents a unique addressable memory ...

Q2(b). A computer has 4 K Word RAM with each memory word of 16 bits. It has cache memory having 8 blocks of size 32 bits (2 memory words). Show how the main memory address (1A9)h will be mapped to the cache address, if

(i)) Direct cache mapping is used (100 words)
(ii)) Associative cache mapping is used (100 words)
(iii)) Two-way set-associative cache mapping is used. You should show the size of the tag, index, main memory block address and offset in your answer. (100 words)

Key Points:

Main memory addresses are 12 bits for 4K words.
Cache block size of 2 words (32 bits) dictates a 1-bit offset.
Direct mapping uses 8-bit Tag, 3-bit Index, 1-bit Offset.
Associative mapping uses 11-bit Tag, 1-bit Offset.

Answer: This question explores different cache mapping techniques using a given memory configuration. The process involves first determining the various address field sizes (tag, index/set, offset) based on the main memory and cache specifications. Then, the provided main memory address is broken down into these fields according to each mapping method. Understanding these distinctions is crucial for efficient memory access and performance optimization in computer systems, as discussed in MCS-012, Block ...

Q2(c). Define the term Interrupt? Why is an interrupt used in a computer? How is an interrupt handled? Explain with the help of a suitable diagram.

Key Points:

Interrupt: Signal to CPU indicating an event requiring immediate attention.
Purpose: Enhances CPU efficiency, system responsiveness, and enables multitasking.
Handling: CPU saves context, executes Interrupt Service Routine (ISR), restores context.
Interrupt Service Routine (ISR): Dedicated software routine for processing specific interrupts.

Answer: An interrupt is a signal, either hardware or software generated, that indicates an event requiring immediate attention from the Central Processing Unit (CPU). It temporarily suspends the CPU's current execution, allowing it to respond to the critical event without delay. This mechanism is fundamental for managing diverse operations within a computer system, as discussed in MCS-012. Interrupts are crucial for several reasons. Firstly, they enhance CPU efficiency by preventing constant polling (b...

Q2(d). What is an Input/Output processor? What are the uses of the Input/Output processor? Explain the structure of the Input/Output processor/channel with the help of a diagram.

Key Points:

An I/O Processor (IOP) is a dedicated processor for managing peripheral operations.
IOPs free the main CPU from routine I/O tasks, enhancing overall system efficiency.
They execute specialized 'channel programs' for independent I/O data transfer.
IOPs enable parallel processing between the main CPU and I/O devices.

Answer: An Input/Output Processor (IOP), often referred to as an I/O channel, is a specialized, independent processor designed to handle the management of input and output operations. Its primary function, as discussed in MCS-012, is to relieve the Central Processing Unit (CPU) from the detailed control of peripheral devices, thereby allowing the CPU to focus on program execution. The IOP has its own set of instructions, known as channel programs, dedicated to controlling I/O processes. The uses of an...

Q2(e). Assume that a disk has 64 tracks, with each track having 32 sectors, and each sector is of size 4 M Bytes. The cluster size in this system can be assumed to be 4 sectors. A file having the name assignmentbca.txt, of size 32 MB, is to be stored on this disk. Assume that it is a new disk, and the first 4 clusters are occupied by the Operating System, and the rest of the clusters are free. How can this file be allotted space on this disk? Also, show the content of FAT after the space allocation to this file. You may make suitable assumptions.

Key Points:

Cluster size is 16 MB (4 sectors * 4 MB/sector).
Total disk has 512 clusters (2048 sectors / 4 sectors/cluster).
File `assignmentbca.txt` (32 MB) requires 2 clusters.
OS occupies clusters 0, 1, 2, 3, making them unavailable.

Answer: To allocate space for the file `assignmentbca.txt` on the given disk, we first need to determine the disk's physical parameters and the file's storage requirements based on the cluster size. First, let's calculate the cluster size and total disk capacity. Each sector is 4 MB, and a cluster consists of 4 sectors. Therefore, the cluster size is 4 sectors × 4 MB/sector = 16 MB. The disk has 64 tracks, with 32 sectors per track, totaling 64 × 32 = 2048 sectors. This means there are 2048 sectors / 4...

Q2(f). Explain the following, giving their uses and advantages/disadvantages, if needed. (Word limit for the answer of each part is 50 words ONLY)

(i)) Latency time of the Hard disk (50 words)
(ii)) Non-impact Printers (50 words)
(iii)) MODEM (50 words)
(iv)) Video Memory (50 words)
(v)) Colour depth of monitors (50 words)
(vi)) Magnetic Tape (50 words)

Key Points:

Hard disk rotational latency is the time for a sector to align with the read/write head.
Non-impact printers (inkjet, laser) print quietly without physical contact, offering high quality.
A MODEM converts digital to analog signals for transmission over telephone lines and vice versa.
Video memory (VRAM) is dedicated RAM on graphics cards for storing display data, accelerating graphics.

Answer:

Q3(a). A single-core uniprocessor system has 32 general-purpose registers. The machine has a RAM of size 64 KB memory words. The size of every general-purpose register and memory word is 32 bits. The computer uses fixed-length instructions of size 32 bits each. An instruction of a machine can have two operands. One of these operands is a direct memory operand, and the other is a register operand. An instruction of a machine consists of bits for the operation code, bits for the memory operand and bits for the register operand. The machine has 32 different operation codes. The machine also has special-purpose registers, which are other than general-purpose registers. These special-purpose registers are Program Counter (PC), Memory Address Register (MAR), Data Register (DR) and Flag registers (FR). The first register among the general-purpose registers can be used as the Accumulator Register. The size of Integer operands on the machine may be assumed to be equal to the size of the accumulator register. To execute instructions, the machine has another special-purpose register called the Instruction Register (IR) of size 32 bits, as each instruction is of this size. Perform the following tasks for the machine. (Make and state suitable assumptions, if any.)

(i)) Design suitable instruction formats for the machine. Specify the size of different fields that are needed in an instruction format. Also, indicate how many bits of an instruction are unused for this machine. Explain your design of the instruction formats. What would be the size of each register? (90 words)
(ii)) Illustrate two valid instructions of the machine by drawing a diagram that shows instructions and related data in registers and memory. (60 words)
(iii)) Assuming that an instruction is first fetched to the Instruction Register (IR), its memory operand is brought to the DR register and the result of an operation is stored in the Accumulator register, write and explain the sequence of micro-operations to fetch and execute a subtraction instruction that subtracts the contents of a memory operand from the contents of a register operand. The result is stored in the accumulator register. Make and state suitable assumptions, if any. (150 words)

Key Points:

Instruction format: 32-bit, with 5-bit opcode, 5-bit register, 16-bit memory address, and 6 unused bits.
Opcode field requires 5 bits to encode 32 distinct operations (2^5 = 32).
Register operand field uses 5 bits to identify one of 32 general-purpose registers (2^5 = 32).
Memory operand field is 16 bits to directly address 64 KB (65,536 words) of RAM.

Q3(b). Assume that you have a machine, as shown in section 3.2.2 of Block 3, having the set of micro-operations as given in Figure 10 on page 62 of Block 3. Consider that R1 and R2 are both 8-bit registers and contain 10010001 and 00100100, respectively. What will be the values of select inputs, carry-in input, and the result of the operation (including carry-out bit) if the following micro-operations are performed on these registers? (For each micro-operation, you may assume the initial value of R1 and R2 as given above)

(i)) Decrement R2 (75 words)
(ii)) Add R1 and R2 (75 words)
(iii)) OR R1 and R2 (75 words)
(iv)) Shift right R1 (75 words)

Key Points:

Micro-operations use select inputs (S2S1S0) and carry-in (C_in) to control ALU functions.
Decrement R2 (00100100 - 1) uses S2S1S0=010, C_in=0, yielding 00100011 with C_out=1.
Addition of R1 and R2 (10010001 + 00100100) uses S2S1S0=001, C_in=0, yielding 10110101 with C_out=0.
Bit-wise OR of R1 and R2 (10010001 OR 00100100) uses S2S1S0=100, C_in=0, yielding 10110101 with C_out=0.

Answer: The provided question requires applying specific micro-operations on 8-bit registers R1 (10010001) and R2 (00100100), referencing the ALU control function select inputs and carry-in values from Figure 10, page 62 of Block 3. For each operation, we determine the select inputs (S2S1S0), the carry-in (C_in), the 8-bit result, and the carry-out (C_out) bit, assuming the initial register values for each part. Figure 10 defines the control signals for the ALU. The operations are performed bit-wise or...

Q4(a). Write a program using 8086 assembly Language (with proper comments) that accepts one digit as input from the keyboard. This digit is converted to its binary equivalent value and stored in the BL register. The program stores the value of BL in the first element of a byte memory array of size 10. It then increments the BL value and stores it in the second location. This process continues, with the BL value being incremented and stored in each subsequent location of the memory array. Make suitable assumptions, if any.

Key Points:

8086 `INT 21h` (DOS services) used for keyboard input (`AH=01h`) and output (`AH=09h`).
ASCII to binary conversion: Subtract `30h` from input character in `AL` (e.g., '5' (35h) becomes 05h).
`BL` register temporarily holds the current binary value to be stored.
Memory array `DB 10 DUP(?)` defines 10 uninitialized byte locations.

Answer: This 8086 assembly language program accepts a single digit from the keyboard, converts it to its binary equivalent, and then populates a 10-element byte array. It initializes the first array element with the converted binary value and subsequently stores incremented values of the digit in the remaining array locations. This demonstrates fundamental 8086 I/O, data manipulation, and memory addressing. First, the `.DATA` segment defines `MSG_PROMPT` for user interaction and `MY_ARRAY` as a byte ar...

Q4(b). What is a FAR procedure call in the 8086 microprocessor? How is it different from a NEAR procedure call in an 8086 microprocessor? Assuming that a stack is used for implementing procedure calls, and three-word parameters are passed to a FAR procedure, explain how they will be passed and accessed in the procedure. You need not write the assembly code but draw the necessary diagrams to illustrate the concept.

Key Points:

FAR call changes both CS and IP registers, transferring control to a different code segment.
NEAR call changes only IP, staying within the same code segment.
FAR call pushes 4 bytes (CS:IP) onto the stack; NEAR pushes 2 bytes (IP).
Parameters are pushed onto the stack in reverse order before a FAR call.

Answer: In the 8086 microprocessor, a FAR procedure call is used when the called procedure resides in a different code segment from the caller, or at an address that cannot be reached by a 16-bit offset within the current segment. When a FAR `CALL` instruction is executed, the current Code Segment (CS) register and Instruction Pointer (IP) register are both pushed onto the stack before transferring control to the new CS:IP address. This differs significantly from a NEAR procedure call. A NEAR call is f...

Q4(c). Explain the following in the context of the 8086 Microprocessor with the help of an example or a diagram:

(i)) Explain the use of CS and IP registers for computing the address of an instruction in the memory and SS and SP registers for computing the address of the top of the stack. (100 words)
(ii)) Explain the use of the following flags - CF, SF, PF, IF (100 words)
(iii)) Explain the Instructions – LEA, CMP, SHR, RCR (100 words)

Key Points:

8086 uses segment:offset (Segment × 10h + Offset) for 20-bit physical address generation.
CS:IP points to the next instruction's address; SS:SP points to the top of the stack's address.
CF indicates unsigned overflow; SF indicates sign; PF indicates even parity of result's lower 8 bits.
IF (Interrupt Enable Flag) controls maskable interrupts: IF=1 enables, IF=0 disables.

Answer: The 8086 microprocessor architecture relies on specific registers and flags to manage memory addressing, process status, and execute instructions efficiently. Understanding these components is fundamental to assembly language programming on the 8086. Address computation uses a segment:offset mechanism, while flags monitor arithmetic and control flow. Instructions like LEA, CMP, SHR, and RCR provide essential data manipulation capabilities.

MCS-012 Solved Assignment — January 2026 / July 2025

Computer Organisation and Assembly Language Programming | IGNOU Bachelor of Computer Applications (BCA)

MCS-012—January 2026 / July 2025

Computer Organisation and Assembly Language Programming

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MCS-012 Assignment Questions — January 2026

Q1(b). Perform the following conversion of numbers:

Q2(a). Refer to the Figure 2(b) on page 8 in Unit 1 of Block 2. Draw the Internal organisation of an 8×4 RAM. Explain all the inputs and outputs of this organisation. Also, answer the following:

Q2(b). A computer has 4 K Word RAM with each memory word of 16 bits. It has cache memory having 8 blocks of size 32 bits (2 memory words). Show how the main memory address (1A9)h will be mapped to the cache address, if

Q2(c). Define the term Interrupt? Why is an interrupt used in a computer? How is an interrupt handled? Explain with the help of a suitable diagram.

Q2(d). What is an Input/Output processor? What are the uses of the Input/Output processor? Explain the structure of the Input/Output processor/channel with the help of a diagram.

Q2(f). Explain the following, giving their uses and advantages/disadvantages, if needed. (Word limit for the answer of each part is 50 words ONLY)

Q4(c). Explain the following in the context of the 8086 Microprocessor with the help of an example or a diagram: